Integrated circuit devices are typically subject to rigorous testing before they are sold or put to their intended use. For example, each integrated circuit device is tested to determine whether or not it meets the specifications for that type of device as determined by the manufacturer.
One example of an integrated circuit device, which is tested prior to its use in commercial applications, is a memory module. Memory modules are subject to testing to determine whether they meet the specifications for those types of devices as specified by the manufacturer. Memory devices are subjected to such tests as pattern testing and parametric tests. Pattern testing of memory devices is an organized method of exercising each memory cell in a memory device to verify its functionality. On the other hand, parametric tests verify operating parameters such as power consumption, standby current, leakage current, voltage levels, and access time.
For testing a fully buffered DIMM, it is necessary to test DRAM devices and a buffer device that both reside on the DIMM. Testing the DRAM devices may be conventionally done by applying a transparent mode of operation of the buffer device, for example as described in U.S. Pat. No. 6,996,749 to Bains et al., the entire contents of which is hereby incorporated by reference. In the transparent mode of operation, the buffer device passes memory commands to individual DRAM devices through a reserve path and verifies the functionalities of the DRAM devices.
Testing the buffer device itself is done by applying a normal mode of operation in which mode the high-speed serial interface of the buffer device is employed and tested.
A problem associated with conventional testing of fully buffered memory modules is that testing of DRAM devices and testing of the buffer device has to be done in separate places. Conventional testing of a fully buffered memory module employs either a tester with two separate testing slots (a first slot for testing a buffer device under a normal mode of operation and a second slot for testing DRAM devices under a transparent mode of operation) or two different testers (first tester for testing a buffer device under a normal mode of operation and a second tester for testing DRAM devices under a transparent mode of operation). This arrangement complicates and lengthens the testing process because it requires two insertions of the memory module into separate testing slots and it also can cause wear on the contacts of the memory modules.